955 search results - page 5 / 191 » Performance optimization of multiple memory architectures fo... |
CASES
2003
ACM
14 years 29 days ago
2003
ACM
The Single Instruction Multiple Data (SIMD) model for fine-grained parallelism was recently extended to support SIMD operations on disjoint vector elements. In this paper we demon...
DAC
1995
ACM
13 years 11 months ago
1995
ACM
High-level synthesis (HLS) has been successfully targeted towards the digital signal processing (DSP) domain. Both application-speci c integrated circuits (ASICs) and application-...
EUROPAR
2010
Springer
13 years 8 months ago
2010
Springer
Abstract. Traditional parallel programming methodologies for improving performance assume cache-based parallel systems. However, new architectures, like the IBM Cyclops-64 (C64), b...
VLSISP
2008
13 years 7 months ago
2008
Digital signal processing (DSP) applications involve processing long streams of input data. It is important to take into account this form of processing when implementing embedded ...
DAC
1996
ACM
13 years 12 months ago
1996
ACM
In this paper we address the problem of code generation for basic blocks in heterogeneous memory-register DSP processors. We propose a new a technique, based on register-transfer ...