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SBCCI
2004
ACM
117views VLSI» more  SBCCI 2004»
14 years 2 months ago
Reducing test time with processor reuse in network-on-chip based systems
This paper proposes a test planning method capable of reusing available processors as test sources and sinks, and the on-chip network as the access mechanism for the test of cores...
Alexandre M. Amory, Érika F. Cota, Marcelo ...
CODES
2007
IEEE
14 years 3 months ago
Ensuring secure program execution in multiprocessor embedded systems: a case study
Multiprocessor SoCs are increasingly deployed in embedded systems with little or no security features built in. Code Injection attacks are one of the most commonly encountered sec...
Krutartha Patel, Sridevan Parameswaran, Seng Lin S...
GPCE
2003
Springer
14 years 2 months ago
A Case for Test-Code Generation in Model-Driven Systems
A primary goal of generative programming and model-driven ent is to raise the level of abstraction at which designers and developers interact with the software systems they are bui...
Matthew J. Rutherford, Alexander L. Wolf
FATES
2004
Springer
14 years 1 months ago
Test Generation Based on Symbolic Specifications
Abstract. Classical state-oriented testing approaches are based on simple machine models such as Labelled Transition Systems (LTSs), in which data is represented by concrete values...
Lars Frantzen, Jan Tretmans, Tim A. C. Willemse
FSTTCS
2005
Springer
14 years 2 months ago
Testing Concurrent Systems: An Interpretation of Intuitionistic Logic
Abstract. We present a natural confluence of higher-order hereditary Harrop formulas (HH formulas), Constraint Logic Programming (CLP, [JL87]), and Concurrent Constraint Programmi...
Radha Jagadeesan, Gopalan Nadathur, Vijay A. Saras...