70 search results - page 10 / 14 » Performance-Driven Interconnect Global Routing |
ISCA
2008
IEEE
13 years 6 months ago
2008
IEEE
Evolving technology and increasing pin-bandwidth motivate the use of high-radix routers to reduce the diameter, latency, and cost of interconnection networks. High-radix networks,...
ICCAD
2004
IEEE
14 years 3 months ago
2004
IEEE
Closed formed expressions for buffered interconnect delay approximation have been around for some time. However, previous approaches assume that buffers are free to be placed anyw...
ICPPW
1999
IEEE
13 years 11 months ago
1999
IEEE
We present a new multiple ring network for multiprocessors, called the Multistage Ring Network(MRN). The MRN has a 2-level hierarchy of register insertion rings, and its interconn...
DATE
2005
IEEE
14 years 9 days ago
2005
IEEE
In this paper, we present an experimental integrated platform for the research, development and evaluation of new VLSI back-end algorithms and design flows. Interconnect scaling ...
IJFCS
2006
13 years 6 months ago
2006
Dynamically reconfigurable architectures offer extremely fast solutions to various problems. The Circuit Switched Tree (CST) is an important interconnect used to implement such ar...