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ASPDAC
2006
ACM
95views Hardware» more  ASPDAC 2006»
14 years 1 months ago
Physical design implementation of segmented buses to reduce communication energy
Abstract— The amount of energy consumed for interconnecting the IP-blocks is increasing significantly due to the suboptimal scaling of long wires. To limit this energy penalty, ...
Jin Guo, Antonis Papanikolaou, Pol Marchal, Franck...
CODES
2003
IEEE
14 years 10 days ago
A modular simulation framework for architectural exploration of on-chip interconnection networks
Ever increasing complexity and heterogeneity of SoC platforms require diversified on-chip communication schemes beyond the currently omnipresent shared bus architectures. To prev...
Tim Kogel, Malte Doerper, Andreas Wieferink, Raine...
FIT
2010
13 years 1 months ago
A survey of services placement mechanisms for future mobile communication networks
Mobile communication networks experience a tremendous growth. According to the vision of Wireless World Research Forum (WWRF), there will be 7 trillion wireless devices serving 7 ...
Shahzad Ali, Andreas Mitschele-Thiel, Ali Diab, Am...
DATE
2009
IEEE
183views Hardware» more  DATE 2009»
14 years 1 months ago
SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips
Three-dimensional integrated circuits are a promising approach to address the integration challenges faced by current Systems on Chips (SoCs). Designing an efficient Network on C...
Ciprian Seiculescu, Srinivasan Murali, Luca Benini...
DAC
2009
ACM
14 years 8 months ago
NoC topology synthesis for supporting shutdown of voltage islands in SoCs
In many Systems on Chips (SoCs), the cores are clustered in to voltage islands. When cores in an island are unused, the entire island can be shutdown to reduce the leakage power c...
Ciprian Seiculescu, Srinivasan Murali, Luca Benini...