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ISLPED
2005
ACM
85views Hardware» more  ISLPED 2005»
14 years 19 days ago
A low-power crossroad switch architecture and its core placement for network-on-chip
As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. The individual components of the...
Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen
VLSID
2000
IEEE
90views VLSI» more  VLSID 2000»
13 years 11 months ago
Performance Analysis of Systems with Multi-Channel Communication Architectures
This paper presents a novel system performance analysis technique to support the design of custom communication architectures for System-on-Chip ICs. Our technique fills a gap in...
Kanishka Lahiri, Sujit Dey, Anand Raghunathan
ISCA
2010
IEEE
214views Hardware» more  ISCA 2010»
14 years 4 days ago
Re-architecting DRAM memory systems with monolithically integrated silicon photonics
The performance of future manycore processors will only scale with the number of integrated cores if there is a corresponding increase in memory bandwidth. Projected scaling of el...
Scott Beamer, Chen Sun, Yong-Jin Kwon, Ajay Joshi,...
COMSNETS
2012
182views more  COMSNETS 2012»
12 years 2 months ago
Hierarchy-aware distributed overlays in data centers using DC2
—Popular online services such as social networks, e-commerce and bidding are routinely hosted in large-scale data centers. Group communication systems (e.g., multicast) and distr...
Karthik Nagaraj, Hitesh Khandelwal, Charles Edwin ...
GECCO
2010
Springer
233views Optimization» more  GECCO 2010»
13 years 12 months ago
Evolutionary-based conflict-free scheduling of collective communications on spidergon NoCs
The Spidergon interconnection network has become popular recently in multiprocessor systems on chips. To the best of our knowledge, algorithms for collective communications (CC) h...
Jirí Jaros, Vaclav Dvorak