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ISVLSI
2007
IEEE
116views VLSI» more  ISVLSI 2007»
14 years 2 months ago
Impact of Process Variations on Carbon Nanotube Bundle Interconnect for Future FPGA Architectures
As CMOS technology continues to scale, copper interconnect (CuI) will hinder the performance and reliability of Field Programmable Gate Arrays (FPGA) motivating the need for alter...
Soumya Eachempati, Narayanan Vijaykrishnan, Arthur...
FPL
2001
Springer
142views Hardware» more  FPL 2001»
14 years 12 days ago
Gigahertz Reconfigurable Computing Using SiGe HBT BiCMOS FPGAs
Field programmable gate arrays (FPGAs) are flexible programmable devices that are used in a wide variety of applications such as network routing, signal processing, pattern recogni...
Bryan S. Goda, Russell P. Kraft, Steven R. Carloug...
ANCS
2005
ACM
14 years 1 months ago
A novel reconfigurable hardware architecture for IP address lookup
IP address lookup is one of the most challenging problems of Internet routers. In this paper, an IP lookup rate of 263 Mlps (Million lookups per second) is achieved using a novel ...
Hamid Fadishei, Morteza Saheb Zamani, Masoud Sabae...
FPGA
2001
ACM
139views FPGA» more  FPGA 2001»
14 years 12 days ago
A memory coherence technique for online transient error recovery of FPGA configurations
The partial reconfiguration feature of some of the currentgeneration Field Programmable Gate Arrays (FPGAs) can improve dependability by detecting and correcting errors in onchip ...
Wei-Je Huang, Edward J. McCluskey
ICCAD
2004
IEEE
114views Hardware» more  ICCAD 2004»
14 years 4 months ago
Simultaneous short-path and long-path timing optimization for FPGAs
This paper presents the Routing Cost Valleys (RCV) algorithm – the first published algorithm that simultaneously optimizes all short- and long-path timing constraints in a Field...
Ryan Fung, Vaughn Betz, William Chow