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» Petascale computing with accelerators
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CF
2010
ACM
14 years 3 months ago
Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cach
As the number of transistors on a chip doubles with every technology generation, the number of on-chip cores also increases rapidly, making possible in a foreseeable future to des...
Pierre Michaud, Yiannakis Sazeides, André S...
ISCA
2010
IEEE
222views Hardware» more  ISCA 2010»
14 years 3 days ago
Cohesion: a hybrid memory model for accelerators
Two broad classes of memory models are available today: models with hardware cache coherence, used in conventional chip multiprocessors, and models that rely upon software to mana...
John H. Kelm, Daniel R. Johnson, William Tuohy, St...
CGF
2002
156views more  CGF 2002»
13 years 10 months ago
Object Space EWA Surface Splatting: A Hardware Accelerated Approach to High Quality Point Rendering
Elliptical weighted average (EWA) surface splatting is a technique for high quality rendering of point-sampled 3D objects. EWA surface splatting renders water-tight surfaces of co...
Liu Ren, Hanspeter Pfister, Matthias Zwicker
ISQED
2008
IEEE
153views Hardware» more  ISQED 2008»
14 years 4 months ago
Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding
Clock meshes have found increasingly wide applications in today’s high-performance IC designs. The inherent routing redundancies associated with clock meshes lead to improved cl...
Xiaoji Ye, Min Zhao, Rajendran Panda, Peng Li, Jia...
SIGCOMM
2006
ACM
14 years 4 months ago
Algorithms to accelerate multiple regular expressions matching for deep packet inspection
There is a growing demand for network devices capable of examining the content of data packets in order to improve network security and provide application-specific services. Most...
Sailesh Kumar, Sarang Dharmapurikar, Fang Yu, Patr...