Sciweavers

24 search results - page 3 / 5
» Phantom-BTB: a virtualized branch target buffer design
Sort
View
ASPLOS
1996
ACM
13 years 11 months ago
Analysis of Branch Prediction Via Data Compression
Branch prediction is an important mechanism in modern microprocessor design. The focus of research in this area has been on designing new branch prediction schemes. In contrast, v...
I-Cheng K. Chen, John T. Coffey, Trevor N. Mudge
HPCA
2002
IEEE
14 years 7 months ago
Power Issues Related to Branch Prediction
This paper explores the role of branch predictor organization in power/energy/performance tradeoffs for processor design. We find that as a general rule, to reduce overall energy ...
Dharmesh Parikh, Kevin Skadron, Yan Zhang, Marco B...
ASPLOS
2006
ACM
14 years 1 months ago
Geiger: monitoring the buffer cache in a virtual machine environment
Virtualization is increasingly being used to address server management and administration issues like flexible resource allocation, service isolation and workload migration. In a...
Stephen T. Jones, Andrea C. Arpaci-Dusseau, Remzi ...
ISCA
1999
IEEE
88views Hardware» more  ISCA 1999»
13 years 11 months ago
A Scalable Front-End Architecture for Fast Instruction Delivery
In the pursuit of instruction-level parallelism, significant demands are placed on a processor's instruction delivery mechanism. Delivering the performance necessary to meet ...
Glenn Reinman, Todd M. Austin, Brad Calder
CODES
2004
IEEE
13 years 11 months ago
Analytical models for leakage power estimation of memory array structures
There is a growing need for accurate power models at the system level. Memory structures such as caches, Branch Target Buffers (BTBs), and register files occupy significant area i...
Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt,...