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DAC
2003
ACM
14 years 1 months ago
Force directed mongrel with physical net constraints
This paper describes a new force directed global placement algorithm that exploits and extends techniques from two leading placers, Force-directed [12] [26] and Mongrel [22]. It c...
Sung-Woo Hur, Tung Cao, Karthik Rajagopal, Yegna P...
ISCAS
2005
IEEE
158views Hardware» more  ISCAS 2005»
14 years 2 months ago
Designing optimized pipelined global interconnects: algorithms and methodology impact
— As across-chip wire delays exceed a clock cycle, interconnect pipelining becomes essential. However, the arbitrary insertion of flip-flops can change the differentials of lat...
Vidyasagar Nookala, Sachin S. Sapatnekar
DAC
2001
ACM
14 years 9 months ago
Analysis of On-Chip Inductance Effects using a Novel Performance Optimization Methodology for Distributed RLC Interconnects
This work presents a new and computationally efficient performance optimization technique for distributed RLC interconnects based on a rigorous delay computation scheme. The new o...
Kaustav Banerjee, Amit Mehrotra
VTC
2010
IEEE
242views Communications» more  VTC 2010»
13 years 6 months ago
A Cross-Layer Design Based on Geographic Information for Cooperative Wireless Networks
—Most of geographic routing approaches in wireless ad hoc and sensor networks do not take into consideration the medium access control (MAC) and physical layers when designing a ...
Teck Aguilar, Mohamed Chedly Ghedira, Syue-Ju Syue...
VLSI
2007
Springer
14 years 2 months ago
Parametric structure-preserving model order reduction
Abstract—Analysis and verification environments for nextgeneration nano-scale RFIC designs must be able to cope with increasing design complexity and to account for new effects,...
Jorge Fernandez Villena, Wil H. A. Schilders, L. M...