192 search results - page 14 / 39 » Pipelined FPGA Adders |
ICMCS
2005
IEEE
14 years 1 months ago
2005
IEEE
The paper presents a high-performance architecture of the bit-plane coder for the embedded block coding algorithm in JPEG 2000. The architecture adopts a pipeline structure and is...
ASYNC
2005
IEEE
14 years 1 months ago
2005
IEEE
We present two novel asynchronous control circuits for domino pipelines. The control circuits are based on GasP circuits, have a minimum cycle time of six gate delays, and compare...
VLSID
1996
IEEE
14 years 2 days ago
1996
IEEE
Existing systolic architectures for the LMS algorithm with delayed coeficient adaptation have large adaptation delay and hence degraded convergence behaviour. This paper presents ...
DSD
2010
IEEE
13 years 8 months ago
2010
IEEE
Low power techniques in a FPGA implementation of the hash function called Luffa are presented in this paper. This hash function is under consideration for adoption as standard. Tw...
ITNG
2007
IEEE
14 years 2 months ago
2007
IEEE
A programmable vector processor and its implementation with a field-programmable gate array (FPGA) are presented. This processor is composed of a vector core and a tightly couple...