192 search results - page 2 / 39 » Pipelined FPGA Adders |
ARITH
1997
IEEE
13 years 11 months ago
1997
IEEE
ASPDAC
2010
ACM
13 years 5 months ago
2010
ACM
Multi-operand adders, which are also found in parallel multipliers, usually consist of the compression trees which reduce the number of operands per a bit to two, and the carrypro...
FPGA
2006
ACM
13 years 10 months ago
2006
ACM
In this paper, we propose a technique to flexibly implement genetic algorithms for various problems on FPGAs. For the purpose, we propose a basic architecture for GA which consist...
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
Because of the growing importance of decimal floating-point (DFP) arithmetic, specifications for it are included in the IEEE Draft Standard for Floating-point Arithmetic (IEEE P75...
FCCM
2007
IEEE
13 years 8 months ago
2007
IEEE
Creating a high throughput sparse matrix vector multiplication (SpMxV) implementation depends on a balanced system design. In this paper, we introduce the innovative SpMxV Solver ...