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ARC
2010
Springer
188views Hardware» more  ARC 2010»
14 years 2 months ago
A Fused Hybrid Floating-Point and Fixed-Point Dot-Product for FPGAs
Dot-products are one of the essential and recurrent building blocks in scientific computing, and often take-up a large proportion of the scientific acceleration circuitry. The ac...
Antonio Roldao Lopes, George A. Constantinides
DATE
2006
IEEE
127views Hardware» more  DATE 2006»
14 years 2 months ago
ASIP architecture for multi-standard wireless terminals
This paper presents the Block Processing Engine (BPE), an Application Specific Instruction-Set Processor (ASIP) explicitly designed for the implementation of multistandard wireles...
Daniele Lo Iacono, J. Zory, Ettore Messina, N. Pia...
ICMCS
2006
IEEE
113views Multimedia» more  ICMCS 2006»
14 years 2 months ago
Enhanced Architectural Support for Variable-Length Decoding
This paper proposes a new architecture for efficient variable-length decoding (VLD) of entropy-coded data for multimedia applications on general-purpose processors. It improves o...
Mohanarajah Sinnathamby, Subramania Sudharsanan, N...
SIPS
2006
IEEE
14 years 2 months ago
Partly Parallel Overlapped Sum-Product Decoder Architectures for Quasi-Cyclic LDPC Codes
Abstract— In this paper, we propose partly parallel architectures based on optimal overlapped sum-product (OSP) decoding. To ensure high throughput and hardware utilization effi...
Ning Chen, Yongmei Dai, Zhiyuan Yan
FPL
2008
Springer
180views Hardware» more  FPL 2008»
13 years 9 months ago
Compiled hardware acceleration of Molecular Dynamics code
The objective of Molecular Dynamics (MD) simulations is to determine the shape of a molecule in a given biomolecular environment. These simulations are very demanding computationa...
Jason R. Villarreal, Walid A. Najjar