192 search results - page 9 / 39 » Pipelined FPGA Adders |
TVLSI
2008
13 years 7 months ago
2008
Most hardware compilers apply loop pipelining to increase the parallelism achieved, but pipelining is restricted to the only innermost level in a nested loop. In this work we exten...
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
— We propose a fast Modular Arithmetic Logic Unit (MALU) that is scalable in the digit size (d) and the field size (k). The datapath of MALU has chains of Carry Save Adders (CSA...
ISCAS
1993
IEEE
14 years 1 days ago
1993
IEEE
– This paper describes an efficient architecture for FIR filters. By exploiting the reduced complexity made possible by the use of sparse powers-of-two coefficients, an FIR ...
DELTA
2008
IEEE
14 years 2 months ago
2008
IEEE
Efficient generation of random and pseudorandom sequences is of great importance to a number of applications [4]. In this paper, an efficient implementation of the Mersenne Twis...
FCCM
2009
IEEE
14 years 2 months ago
2009
IEEE
This paper presents an architecture for FPGA acceleration of quadrature methods used for pricing complex options, such as discrete barrier, Bermudan, and American options. The arc...