417 search results - page 69 / 84 » Pipelining in Multi-Query Optimization |
ISCA
2003
IEEE
14 years 21 days ago
2003
IEEE
Current-generation microprocessors are designed to process instructions with one and two source operands at equal cost. Handling two source operands requires multiple ports for ea...
DATE
2010
IEEE
14 years 15 days ago
2010
IEEE
—In order to solve the challenges in processor design for the next generation wireless communication systems, this paper first proposes a system level design flow for communicati...
ISVLSI
2002
IEEE
14 years 10 days ago
2002
IEEE
An Early Completion technique is developed to significantly increase the throughput of NULL Convention self-timed digital systems without impacting latency or compromising their s...
ACSAC
2000
IEEE
13 years 12 months ago
2000
IEEE
The performance of RSA hardware is primarily determined by an efficient implementation of the long integer modular arithmetic and the ability to utilize the Chinese Remainder The...
HPCA
2000
IEEE
13 years 11 months ago
2000
IEEE
We are attacking the memory bottleneck by building a “smart” memory controller that improves effective memory bandwidth, bus utilization, and cache efficiency by letting appl...