95 search results - page 10 / 19 » Pipelining with Futures |
ASPLOS
2010
ACM
14 years 2 months ago
2010
ACM
As the number of devices available per chip continues to increase, the computational potential of future computer architectures grows likewise. While this is a clear benefit for f...
IPPS
2005
IEEE
14 years 1 months ago
2005
IEEE
As technological process shrinks and clock rate increases, instruction caches can no longer be accessed in one cycle. Alternatives are implementing smaller caches (with higher mis...
NOCS
2007
IEEE
14 years 1 months ago
2007
IEEE
— Microarchitecturally integrated on-chip networks, or micronets, are candidates to replace busses for processor component interconnect in future processor designs. For micronets...
ISCA
1997
IEEE
13 years 11 months ago
1997
IEEE
The performance tradeoff between hardware complexity and clock speed is studied. First, a generic superscalar pipeline is defined. Then the specific areas of register renaming, ...
VVS
2000
IEEE
13 years 12 months ago
2000
IEEE
This paper evaluates and compares four volume rendering algorithms that have become rather popular for rendering datasets described on uniform rectilinear grids: raycasting, splat...