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» Polymorphic On-Chip Networks
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HPCA
2009
IEEE
14 years 8 months ago
Express Cube Topologies for on-Chip Interconnects
Driven by continuing scaling of Moore's law, chip multiprocessors and systems-on-a-chip are expected to grow the core count from dozens today to hundreds in the near future. ...
Boris Grot, Joel Hestness, Stephen W. Keckler, Onu...
NIPS
2004
13 years 9 months ago
On-Chip Compensation of Device-Mismatch Effects in Analog VLSI Neural Networks
Device mismatch in VLSI degrades the accuracy of analog arithmetic circuits and lowers the learning performance of large-scale neural networks implemented in this technology. We s...
Miguel Figueroa, Seth Bridges, Chris Diorio
ASAP
2003
IEEE
108views Hardware» more  ASAP 2003»
14 years 28 days ago
Physical Planning for On-Chip Multiprocessor Networks and Switch Fabrics
On-chip implementation of multiprocessor systems requires the planarization of the interconnect network onto the silicon floorplan. Manual floorplanning approaches will become i...
Terry Tao Ye, Giovanni De Micheli
ICCD
2006
IEEE
137views Hardware» more  ICCD 2006»
14 years 4 months ago
Implementation and Evaluation of On-Chip Network Architectures
— Driven by the need for higher bandwidth and complexity reduction, off-chip interconnect has evolved from proprietary busses to networked architectures. A similar evolution is o...
Paul Gratz, Changkyu Kim, Robert G. McDonald, Step...
NOCS
2008
IEEE
14 years 2 months ago
Real-Time Communication Analysis for On-Chip Networks with Wormhole Switching
Abstract— In this paper, we discuss a real-time on-chip communication service with a priority-based wormhole switching policy. A novel off-line schedulability analysis approach i...
Zheng Shi, Alan Burns