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DAC
2002
ACM
14 years 7 months ago
Exploiting operation level parallelism through dynamically reconfigurable datapaths
Increasing non-recurring engineering (NRE) and mask costs are making it harder to turn to hardwired Application Specific Integrated Circuit (ASIC) solutions for high performance a...
Zhining Huang, Sharad Malik
ARC
2009
Springer
134views Hardware» more  ARC 2009»
13 years 11 months ago
A HyperTransport 3 Physical Layer Interface for FPGAs
Abstract. This paper presents the very first implementation of a HyperTransport 3 physical layer interface for Field Programmable Gate Arrays. HyperTransport is a low latency, high...
Heiner Litz, Holger Fröning, Ulrich Brün...
EH
2000
IEEE
156views Hardware» more  EH 2000»
13 years 11 months ago
Evolution of Analog Circuits on Field Programmable Transistor Arrays
Evolvable Hardware (EHW) refers to HW design and selfreconfiguration using evolutionary/genetic mechanisms. The paper presents an overview of some key concepts of EHW, describing ...
Adrian Stoica, Didier Keymeulen, Ricardo Salem Zeb...
TASE
2010
IEEE
13 years 1 months ago
Intelligent Component-Based Automation of Baggage Handling Systems With IEC 61499
Airport Baggage Handling is a field of automation systems that is currently dependent on centralised control systems and conventional automation programming techniques. In this and...
Geoff Black, Valeriy Vyatkin
TVLSI
2008
121views more  TVLSI 2008»
13 years 6 months ago
Area-Efficient Arithmetic Expression Evaluation Using Deeply Pipelined Floating-Point Cores
Recently, it has become possible to implement floating-point cores on field-programmable gate arrays (FPGAs) to provide acceleration for the myriad applications that require high-p...
Ronald Scrofano, Ling Zhuo, Viktor K. Prasanna