35 search results - page 3 / 7 » Power - Performance Optimization for Custom Digital Circuits |
DAC
2000
ACM
14 years 8 months ago
2000
ACM
Custom design, in which the designer controls the physical structure of the chip, can greatly improve the speed, power, and delay of an ASIC chip without affecting design time. Th...
CEC
2003
IEEE
14 years 1 months ago
2003
IEEE
In this paper, the use of Simulated Evolution (SimE) Algorithm in the design of digital logic circuits is proposed. SimE algorithm consists of three steps: evaluation, selection an...
FPGA
2004
ACM
14 years 1 months ago
2004
ACM
We consider active leakage power dissipation in FPGAs and present a “no cost” approach for active leakage reduction. It is well-known that the leakage power consumed by a digi...
IRI
2007
IEEE
14 years 2 months ago
2007
IEEE
The paper presents a technique for the design of digital systems on the basis of reusable hardware templates, which are circuits with modifiable functionality that might be custom...
DATE
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper suggests a practical “hybrid” synthesis methodology which integrates designer-derived analytical models for system-level description with simulation-based models at...