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DATE
2006
IEEE
98views Hardware» more  DATE 2006»
14 years 3 months ago
Power-constrained test scheduling for multi-clock domain SoCs
This paper presents a wrapper and test access mechanism design for multi-clock domain SoCs that consists of cores with different clock frequencies during test. We also propose a t...
Tomokazu Yoneda, Kimihiko Masuda, Hideo Fujiwara
BMCBI
2006
90views more  BMCBI 2006»
13 years 10 months ago
The PowerAtlas: a power and sample size atlas for microarray experimental design and research
Background: Microarrays permit biologists to simultaneously measure the mRNA abundance of thousands of genes. An important issue facing investigators planning microarray experimen...
Grier P. Page, Jode W. Edwards, Gary L. Gadbury, P...
CSDA
2007
159views more  CSDA 2007»
13 years 9 months ago
Multivariate out-of-sample tests for Granger causality
A time series is said to Granger cause another series if it has incremental predictive power when forecasting it. While Granger causality tests have been studied extensively in th...
Sarah Gelper, Christophe Croux
TC
2008
13 years 9 months ago
Low-Transition Test Pattern Generation for BIST-Based Applications
A low-transition test pattern generator, called the low-transition linear feedback shift register (LT-LFSR), is proposed to reduce the average and peak power of a circuit during te...
Mehrdad Nourani, Mohammad Tehranipoor, Nisar Ahmed
VLSID
2002
IEEE
131views VLSI» more  VLSID 2002»
14 years 10 months ago
Divide-and-Conquer IDDQ Testing for Core-Based System Chips
IDDQ testing has been used as a test technique to supplement voltage testing of CMOS chips. The idea behind IDDQ testing is to declare a chip as faulty if the steady-state current...
C. P. Ravikumar, Rahul Kumar