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ASPDAC
2007
ACM
107views Hardware» more  ASPDAC 2007»
14 years 1 months ago
A Technique to Reduce Peak Current and Average Power Dissipation in Scan Designs by Limited Capture
Abstract-- In this paper, a technique that can efficiently reduce peak and average switching activity during test application is proposed. The proposed method does not require any ...
Seongmoon Wang, Wenlong Wei
FLAIRS
2004
13 years 11 months ago
The Power of Experience: On the Usefulness of Validation Knowledge
TURING Test technologies are promising ways to validate AI systems which may have no alternative way to indicate validity. Human experts (validators) are often too expensive to in...
Rainer Knauf, Setsuo Tsuruta, Kenichi Uehara, Taka...
SBCCI
2005
ACM
86views VLSI» more  SBCCI 2005»
14 years 3 months ago
Ultra-low power CMOS cells for temperature sensors
Temperature sensors and voltage references require cells that generate both PTAT (Proportional To Absolute Temperature) and NTC (Negative Temperature Coefficient) voltages. We pre...
Conrado Rossi, Pablo Aguirre
ATS
2005
IEEE
191views Hardware» more  ATS 2005»
14 years 3 months ago
Low Transition LFSR for BIST-Based Applications
Abstract—This paper presents a low transition test pattern generator, called LT-LFSR, to reduce average and peak power of a circuit during test by reducing the transitions within...
Mohammad Tehranipoor, Mehrdad Nourani, Nisar Ahmed
FPL
2004
Springer
98views Hardware» more  FPL 2004»
14 years 3 months ago
Power-Driven Design Partitioning
In order to enable efficient integration of FPGAs into cost effective and reliable high-performance systems as well potentially into low power mobile systems, their power efficienc...
Rajarshi Mukherjee, Seda Ogrenci Memik