1419 search results - page 6 / 284 » Power Droop Testing |
DATE
2008
IEEE
14 years 4 months ago
2008
IEEE
Abstract—Wafer-level test during burn-in (WLTBI) has recently emerged as a promising technique to reduce test and burn-in costs in semiconductor manufacturing. However, the testi...
CAV
2012
Springer
12 years 7 days ago
2012
Springer
The growing complexity of hardware optimizations employed by multiprocessors leads to subtle distinctions among allowed and disallowed behaviors, posing challenges in specifying th...
TCAD
2002
13 years 9 months ago
2002
Test scheduling is an important problem in system-on-a-chip (SOC) test automation. Efficient test schedules minimize the overall system test application time, avoid test resource c...
ICCD
2003
IEEE
14 years 3 months ago
2003
IEEE
We present a test scheduling methodology for core-based system-on-chips that allows tradeoff between system power dissipation and overall test time. The basic strategy is to use t...
ASPDAC
2006
ACM
14 years 3 months ago
2006
ACM
Abstract— For scan-based testing, the high test power consumption may cause test power management problems, and the extra scan chain connections may cause routability degradation...