462 search results - page 15 / 93 » Power Efficient Data Cache Designs |
CODES
2011
IEEE
12 years 7 months ago
2011
IEEE
Today, mobile smartphones are expected to be able to run the same complex, memory-intensive applications that were originally designed and coded for general-purpose processors. Ho...
ISLPED
2010
ACM
13 years 7 months ago
2010
ACM
Runtime characteristics of individual threads (such as IPC, cache usage, etc.) are a critical factor in making efficient scheduling decisions in modern chip-multiprocessor systems...
ASPLOS
2008
ACM
13 years 9 months ago
2008
ACM
Integrating more processor cores on-die has become the unanimous trend in the microprocessor industry. Most of the current research thrusts using chip multiprocessors (CMPs) as th...
HPCA
2008
IEEE
14 years 7 months ago
2008
IEEE
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache ...
MICRO
2006
IEEE
14 years 1 months ago
2006
IEEE
This paper presents and studies a distributed L2 cache management approach through OS-level page allocation for future many-core processors. L2 cache management is a crucial multi...