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TC
2010
13 years 6 months ago
Design and Analysis of On-Chip Networks for Large-Scale Cache Systems
—Switched networks have been adopted in on-chip communication for their scalability and efficient resource sharing. However, using a general network for a specific domain may res...
Yuho Jin, Eun Jung Kim, Ki Hwan Yum
ISCAS
2007
IEEE
106views Hardware» more  ISCAS 2007»
14 years 2 months ago
Area-Power Efficient Lifting-Based DWT Hardware for Implantable Neuroprosthetics
— Discrete wavelet transform (DWT) has been shown to provide exceptionally efficient data compression for neural records. This paper describes an area-power minimized hardware im...
Awais M. Kamboh, Matthew Raetz, Andrew Mason, Kari...
ISSS
2000
IEEE
91views Hardware» more  ISSS 2000»
14 years 25 days ago
Instruction-based System-level Power Evaluation of System-On-A-Chip Peripheral Cores
Various system-level core-based power evaluation approaches for core types like microprocessors, caches, main memories, and buses, have been proposed in the past. Approaches for o...
Tony Givargis, Frank Vahid, Jörg Henkel
ICDE
2004
IEEE
118views Database» more  ICDE 2004»
14 years 9 months ago
A Peer-to-peer Framework for Caching Range Queries
Peer-to-peer systems are mainly used for object sharing although they can provide the infrastructure for many other applications. In this paper, we extend the idea of object shari...
Ozgur D. Sahin, Abhishek Gupta, Divyakant Agrawal,...
HPCA
2004
IEEE
14 years 8 months ago
Accurate and Complexity-Effective Spatial Pattern Prediction
Recent research suggests that there are large variations in a cache's spatial usage, both within and across programs. Unfortunately, conventional caches typically employ fixe...
Chi F. Chen, Se-Hyun Yang, Babak Falsafi, Andreas ...