462 search results - page 35 / 93 » Power Efficient Data Cache Designs |
HPCA
2005
IEEE
14 years 2 months ago
2005
IEEE
Future high-performance billion-transistor processors are likely to employ partitioned architectures to achieve high clock speeds, high parallelism, low design complexity, and low...
VTC
2007
IEEE
14 years 2 months ago
2007
IEEE
— The characterization of downlink traffic power is an important issue for the design of efficient call admission control (CAC) and radio resource management (RRM) procedures. In...
ECRTS
2007
IEEE
14 years 2 months ago
2007
IEEE
Of late, there has been a considerable interest in models, algorithms and methodologies specifically targeted towards designing hardware and software for streaming applications. ...
ISCA
2010
IEEE
14 years 1 months ago
2010
IEEE
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
ISPAN
2000
IEEE
14 years 26 days ago
2000
IEEE
We present new architectural concepts for uniprocessor designs that conform to the data-driven computation paradigm. Usage of our D2 -CPU (Data-Driven processor) follows the natura...