462 search results - page 47 / 93 » Power Efficient Data Cache Designs |
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
HPCA
2011
IEEE
12 years 11 months ago
2011
IEEE
Traditional architectural designs are normally focused on CPUs and have been often decoupled from I/O considerations. They are inefficient for high-speed network processing with a...
ICCAD
1994
IEEE
13 years 11 months ago
1994
IEEE
We present an improved data model that reflects the whole VLSI design process including bottom-up and topdown design phases. The kernel of the model is a static version concept th...
DAC
2010
ACM
13 years 7 months ago
2010
ACM
Leveraging the power of nowadays graphics processing units for robust power grid simulation remains a challenging task. Existing preconditioned iterative methods that require inco...
SSDBM
1999
IEEE
13 years 11 months ago
1999
IEEE
In many scientific domains, experimental devices or simulation programs generate large volumes of data. The volumes of data may reach hundreds of terabytes and therefore it is imp...