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DATE
2006
IEEE
89views Hardware» more  DATE 2006»
16 years 8 days ago
Automatic insertion of low power annotations in RTL for pipelined microprocessors
We propose instruction-driven slicing, a new technique for annotating microprocessor descriptions at the Register Transfer Level (RTL) in order to achieve lower power dissipation....
Vinod Viswanath, Jacob A. Abraham, Warren A. Hunt ...
SAC
2008
ACM
15 years 5 months ago
Filtering drowsy instruction cache to achieve better efficiency
Leakage power in cache memories represents a sizable fraction of total power consumption, and many techniques have been proposed to reduce it. As a matter of fact, during a fixed ...
Roberto Giorgi, Paolo Bennati
ASAP
2009
IEEE
143views Hardware» more  ASAP 2009»
16 years 3 months ago
Scalar Processing Overhead on SIMD-Only Architectures
—The Cell processor consists of a general-purpose core and eight cores with a complete SIMD instruction set. Although originally designed for multimedia and gaming, it is current...
Arnaldo Azevedo Filho, Ben H. H. Juurlink
DAC
1999
ACM
15 years 10 months ago
Power Conscious Fixed Priority Scheduling for Hard Real-Time Systems
Power efficient design of real-time systems based on programmable processors becomes more important as system functionality is increasingly realized through software. This paper ...
Youngsoo Shin, Kiyoung Choi
VLSI
2012
Springer
14 years 1 months ago
A Signature-Based Power Model for MPSoC on FPGA
e technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction than, for example, commonly used instruction-set sim...
Roberta Piscitelli, Andy D. Pimentel