1238 search results - page 239 / 248 » Power Efficient Processor Architecture and The Cell Processo... |
NIXDORF
1992
13 years 11 months ago
1992
We present some quantitative performance measurements for the computing power of Programmable Active Memories (PAM), as introduced by [2]. Based on Field Programmable Gate Array (...
DAC
2010
ACM
13 years 11 months ago
2010
ACM
We present a methodology for off-chip memory bandwidth minimization through application-driven L2 cache partitioning in multicore systems. A major challenge with multi-core system...
CASES
2005
ACM
13 years 9 months ago
2005
ACM
Digital Signal Processing (DSP) is becoming increasingly widespread in portable devices. Due to harsh constraints on power, latency, and throughput in embedded environments, devel...
WACV
2008
IEEE
14 years 1 months ago
2008
IEEE
deliver objects, handle emergency, wherever he/she is inside the home. In addition, the burden of processing We address issues dealing with distributed visual power can be distribu...
HPCA
2009
IEEE
14 years 8 months ago
2009
IEEE
In a Chip Multi-Processor (CMP) with private caches, the last level cache is statically partitioned between all the cores. This prevents such CMPs from sharing cache capacity in r...