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» Power Efficient Processor Architecture and The Cell Processo...
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CF
2004
ACM
15 years 11 months ago
The happy marriage of architecture and application in next-generation reconfigurable systems
New applications and standards are first conceived only for functional correctness and without concerns for the target architecture. The next challenge is to map them onto an arch...
Ingrid Verbauwhede, Patrick Schaumont
PACS
2000
Springer
110views Hardware» more  PACS 2000»
15 years 9 months ago
Compiler-Directed Dynamic Frequency and Voltage Scheduling
Dynamic voltage and frequency scaling has been identified as one of the most effective ways to reduce power dissipation. This paper discusses a compilation strategy that identifies...
Chung-Hsing Hsu, Ulrich Kremer, Michael S. Hsiao
ASPDAC
2007
ACM
95views Hardware» more  ASPDAC 2007»
15 years 10 months ago
Low Power Techniques for Mobile Application SoCs Based on Integrated Platform "UniPhier"
In this Paper, we describe the various low power techniques for mobile application SoCs based on the integrated platform "UniPhier". To minimize SoC power dissipation, h...
Masaitsu Nakajima, Takao Yamamoto, Masayuki Yamasa...
ICPP
2009
IEEE
16 years 23 days ago
Analysis of Parallel Algorithms for Energy Conservation in Scalable Multicore Architectures
Abstract—This paper analyzes energy characteristics of parallel algorithms executed on scalable multicore processors. Specifically, we provide a methodology for evaluating energ...
Vijay Anand Korthikanti, Gul Agha
166
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VLSID
2005
IEEE
129views VLSI» more  VLSID 2005»
16 years 6 months ago
A RISC Hardware Platform for Low Power Java
Java is increasingly being used as a language and binary format for low power, embedded systems. Current software only approaches to Java execution do not always suit the type of ...
Paul Capewell, Ian Watson