Sciweavers

296 search results - page 31 / 60
» Power Estimation in Sequential Circuits
Sort
View
FPGA
2009
ACM
183views FPGA» more  FPGA 2009»
14 years 2 months ago
A comparison of via-programmable gate array logic cell circuits
Via-programmable gate arrays (VPGAs) offer a middle ground between application specific integrated circuits and field programmable gate arrays in terms of flexibility, manufac...
Thomas C. P. Chau, Philip Heng Wai Leong, Sam M. H...
ISLPED
2006
ACM
83views Hardware» more  ISLPED 2006»
14 years 2 months ago
Considering process variations during system-level power analysis
Process variations will increasingly impact the operational characteristics of integrated circuits in nanoscale semiconductor technologies. Researchers have proposed various desig...
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan...
ASPDAC
2006
ACM
157views Hardware» more  ASPDAC 2006»
14 years 2 months ago
Delay modeling and static timing analysis for MTCMOS circuits
- One of the critical issues in MTCMOS design is how to estimate a circuit delay quickly. In this paper, we propose a delay modeling and static timing analysis (STA) methodology ta...
Naoaki Ohkubo, Kimiyoshi Usami
ATS
1997
IEEE
89views Hardware» more  ATS 1997»
14 years 7 days ago
Guaranteeing Testability in Re-encoding for Low Power
This paper considers the testability implications of low power design methodologies. Low power and high testability are shown to be highly contrasting requirements, and an optimiz...
Silvia Chiusano, Fulvio Corno, Paolo Prinetto, Mau...
DAC
1999
ACM
14 years 9 months ago
A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design
We propose a method for power optimization that considers glitch reduction by gate sizing based on the statistical estimation of glitch transitions. Our method reduces not only th...
Masanori Hashimoto, Hidetoshi Onodera, Keikichi Ta...