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» Power Estimation in Sequential Circuits
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VTS
2005
IEEE
97views Hardware» more  VTS 2005»
14 years 1 months ago
Static Compaction of Delay Tests Considering Power Supply Noise
Excessive power supply noise can lead to overkill during delay test. A static compaction algorithm is described in this paper that prevents such overkill. A power supply noise est...
Jing Wang 0006, Xiang Lu, Wangqi Qiu, Ziding Yue, ...
DSD
2008
IEEE
85views Hardware» more  DSD 2008»
14 years 2 months ago
TASTE: Testability Analysis Engine and Opened Libraries for Digital Data Path
Testability is one of the most important factors that are considered during design cycle along with reliability, speed, power consumption, cost and other factors important for a c...
Josef Strnadel
IOLTS
2005
IEEE
141views Hardware» more  IOLTS 2005»
14 years 1 months ago
A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning
With the aggressive scaling of the CMOS technology parametric variation of the transistor threshold voltage causes significant spread in the circuit delay as well as leakage spect...
Arijit Raychowdhury, Swaroop Ghosh, Kaushik Roy
PCM
2004
Springer
113views Multimedia» more  PCM 2004»
14 years 1 months ago
Low-Power Video Decoding for Mobile Multimedia Applications
This paper proposes a novel low-power video decoding scheme. In the encoded video bitstream, there are quite a large number of non-coded blocks. When the number of the non-coded bl...
Seongsoo Lee, Min-Cheol Hong
HOST
2008
IEEE
14 years 2 months ago
Slicing Up a Perfect Hardware Masking Scheme
—Masking is a side-channel countermeasure that randomizes side-channel leakage, such as the power dissipation of a circuit. Masking is only effective on the condition that the in...
Zhimin Chen, Patrick Schaumont