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» Power Estimation in Sequential Circuits
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ICCAD
2006
IEEE
111views Hardware» more  ICCAD 2006»
14 years 4 months ago
State re-encoding for peak current minimization
In a synchronous finite state machine (FSM), huge current peaks are often observed at the moment of state transition. Previous low power state encoding algorithms focus on the red...
Shih-Hsu Huang, Chia-Ming Chang, Yow-Tyng Nieh
CF
2004
ACM
14 years 1 months ago
Designing and testing fault-tolerant techniques for SRAM-based FPGAs
This paper discusses fault-tolerant techniques for SRAM-based FPGAs. These techniques can be based on circuit level modifications, with obvious modifications in the programmable a...
Fernanda Lima Kastensmidt, Gustavo Neuberger, Luig...
TABLEAUX
1998
Springer
14 years 4 days ago
Model Checking: Historical Perspective and Example (Extended Abstract)
ple (Extended Abstract) Edmund M. Clarke and Sergey Berezin Carnegie Mellon University -- USA Model checking is an automatic verification technique for finite state concurrent syst...
Edmund M. Clarke, Sergey Berezin
CASES
2008
ACM
13 years 10 months ago
Compiling custom instructions onto expression-grained reconfigurable architectures
While customizable processors aim at combining the flexibility of general purpose processors with the speed and power advantages of custom circuits, commercially available process...
Paolo Bonzini, Giovanni Ansaloni, Laura Pozzi
TE
2010
104views more  TE 2010»
13 years 2 months ago
Integrating Asynchronous Digital Design Into the Computer Engineering Curriculum
Abstract--As demand increases for circuits with higher performance, higher complexity, and decreased feature size, asynchronous (clockless) paradigms will become more widely used i...
Scott C. Smith, Waleed Al-Assadi, Jia Di