296 search results - page 6 / 60 » Power Estimation in Sequential Circuits |
ICCAD
2004
IEEE
14 years 5 months ago
2004
IEEE
28
Voted
ISLPED
1995
ACM
13 years 11 months ago
1995
ACM
We present a transistor level power estimator which exploits algorithms for fast circuit simulation to compute the power dissipation of CMOS circuits. The proposed approach uses s...
MTV
2007
IEEE
14 years 2 months ago
2007
IEEE
Test vector ordering is recognized as a simple and non-intrusive approach to assist test power reduction. Simulation based test vector ordering approach to minimize circuit transit...
DAC
2005
ACM
14 years 9 months ago
2005
ACM
In this work, we propose a new paradigm called power emulation, which exploits hardware acceleration to drastically speedup power estimation. Power emulation is based on the obser...
DAC
1997
ACM
14 years 8 days ago
1997
ACM
A modeling approach is presented that captures the dependence of the power dissipation of a combinational logic circuit on its input output signal switching activity. The resulting...