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FPL
2006
Springer
127views Hardware» more  FPL 2006»
13 years 10 months ago
On-FPGA Communication Architectures and Design Factors
The recent development of Platform-FPGA or FieldProgrammable System-on-Chip architectures, with immersed coarse-grain processors, embedded memories and IP cores, offers the potent...
Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. C...
DATE
2008
IEEE
115views Hardware» more  DATE 2008»
14 years 1 months ago
Improving the Efficiency of Run Time Reconfigurable Devices by Configuration Locking
Run-time reconfigurable logic is a very attractive alterative in the design of SoC. However, configuration overhead can largely decrease the system performance. In this work, we p...
Yang Qu, Juha-Pekka Soininen, Jari Nurmi
CODES
2005
IEEE
14 years 10 days ago
Aggregating processor free time for energy reduction
Even after carefully tuning the memory characteristics to the application properties and the processor speed, during the execution of real applications there are times when the pr...
Aviral Shrivastava, Eugene Earlie, Nikil D. Dutt, ...
CODES
2005
IEEE
14 years 10 days ago
Enhancing security through hardware-assisted run-time validation of program data properties
The growing number of information security breaches in electronic and computing systems calls for new design paradigms that consider security as a primary design objective. This i...
Divya Arora, Anand Raghunathan, Srivaths Ravi, Nir...
ICASSP
2011
IEEE
12 years 10 months ago
A simplified Subspace Gaussian Mixture to compact acoustic models for speech recognition
Speech recognition applications are known to require a significant amount of resources (memory, computing power). However, embedded speech recognition systems, such as in mobile p...
Mohamed Bouallegue, Driss Matrouf, Georges Linares