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» Power Macromodeling for High Level Power Estimation
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ISCAS
2008
IEEE
115views Hardware» more  ISCAS 2008»
14 years 2 months ago
FSMD partitioning for low power using simulated annealing
— It is well known that significant power savings can be obtained by disabling or shutting down parts of a circuit during idle periods. One method is to use a high level partiti...
Nainesh Agarwal, Nikitas J. Dimopoulos
ISCAS
1999
IEEE
87views Hardware» more  ISCAS 1999»
13 years 12 months ago
Instruction level power model of microcontrollers
In the design of low power systems, it is important to analyze and optimize both the hardware and the software component of the system. To evaluate the software component of the s...
C. Chakrabarti, D. Gaitonde
BMCBI
2006
90views more  BMCBI 2006»
13 years 7 months ago
The PowerAtlas: a power and sample size atlas for microarray experimental design and research
Background: Microarrays permit biologists to simultaneously measure the mRNA abundance of thousands of genes. An important issue facing investigators planning microarray experimen...
Grier P. Page, Jode W. Edwards, Gary L. Gadbury, P...
ISLPED
1997
ACM
81views Hardware» more  ISLPED 1997»
13 years 12 months ago
A method of redundant clocking detection and power reduction at RT level design
This paper proposes a novel method to estimate and to reduce redundant power of synchronous circuits at RT level design. Because much redundant power is caused by redundant clocki...
Mitsuhisa Ohnishi, Akihisa Yamada, Hiroaki Noda, T...
ICCAD
1994
IEEE
144views Hardware» more  ICCAD 1994»
13 years 11 months ago
Power analysis of embedded software: a first step towards software power minimization
Embedded computer systems are characterized by the presence of a dedicated processor and the software that runs on it. Power constraints are increasingly becoming the critical com...
Vivek Tiwari, Sharad Malik, Andrew Wolfe