Within this paper the gate-level power-simulation tool GliPS (Glitch Power Simulator) is presented, which gives excellent accuracy (in the range of transistor-level simulators) at...
Dirk Rabe, Gerd Jochens, Lars Kruse, Wolfgang Nebe...
This paper discusses an automated method to build scan chains at the register-transfer level (RTL) for powerconstrained at-speed testing. By analyzing a circuit at the RTL, where ...
A geometric framework for image scale space, enhancement, and segmentation is presented. We consider intensity images as surfaces in the (x I) space. The image is thereby a 2D surf...
We present a functional DBPL in the style of FP that facilitates the definition of precise semantics and opens up opportunities for far-reaching optimizations. The language is int...
Reo is a language for coordinating autonomous components in distributed environments. Coordination in Reo is performed by circuit-like connectors, which are constructed from primi...
Christian Koehler, Alexander Lazovik, Farhad Arbab