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» Power Macromodeling for High Level Power Estimation
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DATE
1998
IEEE
75views Hardware» more  DATE 1998»
14 years 3 hour ago
Power-Simulation of Cell Based ASICs: Accuracy- and Performance Trade-Offs
Within this paper the gate-level power-simulation tool GliPS (Glitch Power Simulator) is presented, which gives excellent accuracy (in the range of transistor-level simulators) at...
Dirk Rabe, Gerd Jochens, Lars Kruse, Wolfgang Nebe...
ICCD
2006
IEEE
116views Hardware» more  ICCD 2006»
14 years 4 months ago
RTL Scan Design for Skewed-Load At-speed Test under Power Constraints
This paper discusses an automated method to build scan chains at the register-transfer level (RTL) for powerconstrained at-speed testing. By analyzing a circuit at the RTL, where ...
Ho Fai Ko, Nicola Nicolici
SCALESPACE
1997
Springer
13 years 12 months ago
From High Energy Physics to Low Level Vision
A geometric framework for image scale space, enhancement, and segmentation is presented. We consider intensity images as surfaces in the (x I) space. The image is thereby a 2D surf...
Ron Kimmel, Nir A. Sochen, Ravi Malladi
DBPL
1991
Springer
76views Database» more  DBPL 1991»
13 years 11 months ago
A Functional DBPL Revealing High Level Optimizations
We present a functional DBPL in the style of FP that facilitates the definition of precise semantics and opens up opportunities for far-reaching optimizations. The language is int...
Martin Erwig, Udo W. Lipeck
ENTCS
2008
131views more  ENTCS 2008»
13 years 7 months ago
Connector Rewriting with High-Level Replacement Systems
Reo is a language for coordinating autonomous components in distributed environments. Coordination in Reo is performed by circuit-like connectors, which are constructed from primi...
Christian Koehler, Alexander Lazovik, Farhad Arbab