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» Power Macromodeling for High Level Power Estimation
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ICCAD
2001
IEEE
128views Hardware» more  ICCAD 2001»
14 years 4 months ago
An Assembly-Level Execution-Time Model for Pipelined Architectures
The aim of this work is to provide an elegant and accurate static execution timing model for 32-bit microprocessor instruction sets, covering also inter–instruction effects. Suc...
Giovanni Beltrame, Carlo Brandolese, William Forna...
ICCAD
2009
IEEE
136views Hardware» more  ICCAD 2009»
13 years 5 months ago
Multi-functional interconnect co-optimization for fast and reliable 3D stacked ICs
Heat removal and power delivery have become two major reliability concerns in 3D stacked IC technology. For thermal problem, two possible solutions exist: thermal-through-silicon-...
Young-Joon Lee, Rohan Goel, Sung Kyu Lim
EH
2004
IEEE
117views Hardware» more  EH 2004»
13 years 11 months ago
Multi-objective Optimization of a Parameterized VLIW Architecture
The use of Application Specific Instruction-set Processors (ASIP) in embedded systems is a solution to the problem of increasing complexity in the functions these systems have to ...
Giuseppe Ascia, Vincenzo Catania, Maurizio Palesi,...
JSAC
2007
200views more  JSAC 2007»
13 years 7 months ago
Analysis of DSRC Service Over-Reach inside an Arched Tunnel
— In this paper, the prediction of received power in the out-of-zone of a Dedicated Short Range Communications (DSRC) system operating inside a typical arched highway tunnel is d...
Gilbert Siy Ching, Mir Ghoraishi, Navarat Lertsiri...
ISCAS
2007
IEEE
112views Hardware» more  ISCAS 2007»
14 years 2 months ago
A New Statistical Approach for Glitch Estimation in Combinational Circuits
— Low-power consumption has become a highly important concern for synchronous standard-cell design, and consequently mandates the use of low-power design methodologies and techni...
Ahmed Sayed, Hussain Al-Asaad