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ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
14 years 14 days ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
PC
2010
196views Management» more  PC 2010»
13 years 5 months ago
Solving path problems on the GPU
We consider the computation of shortest paths on Graphic Processing Units (GPUs). The blocked recursive elimination strategy we use is applicable to a class of algorithms (such as...
Aydin Buluç, John R. Gilbert, Ceren Budak
WIOPT
2010
IEEE
13 years 5 months ago
Resource allocation for cross-layer utility maximization in multi-hop wireless networks in the presence of self interference
Abstract—The cross-layer utility maximization problem subject to stability constraints is considered for a multi-hop wireless network. A time slotted network, where the channel g...
Chathuranga Weeraddana, Marian Codreanu, Matti Lat...
PLDI
2005
ACM
14 years 28 days ago
Register allocation for software pipelined multi-dimensional loops
Software pipelining of a multi-dimensional loop is an important optimization that overlaps the execution of successive outermost loop iterations to explore instruction-level paral...
Hongbo Rong, Alban Douillet, Guang R. Gao
ATAL
2007
Springer
13 years 11 months ago
A unified framework for multi-agent agreement
Multi-Agent Agreement problems (MAP) - the ability of a population of agents to search out and converge on a common state - are central issues in many multi-agent settings, from d...
Kiran Lakkaraju, Les Gasser