111 search results - page 3 / 23 » Power Optimization in Current Mode Circuits |
ISPD
2004
ACM
14 years 1 months ago
2004
ACM
High performance integrated circuits are now reaching the 100-plus watt regime, and power delivery and power grid signal integrity have become critical. Analyzing the performance ...
DATE
2002
IEEE
14 years 25 days ago
2002
IEEE
We present a Dynamic VTH Scaling (DVTS) scheme to save the leakage power during active mode of the circuit. The power saving strategy of DVTS is similar to that of the Dynamic VDD...
ISVLSI
2007
IEEE
14 years 2 months ago
2007
IEEE
In this paper, the problem of sizing MOS Current Mode Logic (MCML) circuits is addressed. The Pareto front is introduced as a useful analysis tool to explore the design space of e...
ICCD
2007
IEEE
14 years 4 months ago
2007
IEEE
In this paper, we propose a novel on-chip voltage drop reduction technique for on-chip power delivery networks of VLSI systems in the presence of variational leakage current sourc...
ICCAD
2002
IEEE
14 years 4 months ago
2002
IEEE
Approaches to achieve low-power and high-speed VLSI's are described with the emphasis on techniques across multiple technology and design levels. To suppress the leakage curr...