430 search results - page 13 / 86 » Power Optimized Combinational Logic Design |
DAC
2003
ACM
14 years 8 months ago
2003
ACM
Combinational circuits are generally thought of as acyclic structures. It is known that cyclic structures can be combinational, and techniques have been proposed to analyze cyclic...
FPGA
2006
ACM
13 years 11 months ago
2006
ACM
This report describes a preliminary evaluation of possible performance of an FPGA-like architecture for future hybrid "CMOL" circuits which combine a semiconductor-trans...
WSC
1998
13 years 9 months ago
1998
The Time Warp protocol is considered to be an effective synchronization mechanism for parallel discrete event simulation (PDES). However, it is widely recognized that it suffers o...
VLSID
2003
IEEE
14 years 8 months ago
2003
IEEE
This paper combines an adaptive supply-voltage scheme with self-timed CMOS digital design, to achieve low power performance. The supply-voltage automatically tracks the input data...
INFOCOM
2003
IEEE
14 years 1 months ago
2003
IEEE
—In this paper, we formulate an optimization problem for the design of light-tree based logical topology in Wavelength Division Multiplexing (WDM) networks. The problem is compri...