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» Power Optimized Combinational Logic Design
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ICCAD
2004
IEEE
113views Hardware» more  ICCAD 2004»
14 years 4 months ago
Vdd programmability to reduce FPGA interconnect power
Power is an increasingly important design constraint for FPGAs in nanometer technologies. Because interconnect power is dominant in FPGAs, we design Vdd-programmable interconnect ...
Fei Li, Yan Lin, Lei He
DAC
1995
ACM
13 years 11 months ago
Efficient Power Estimation for Highly Correlated Input Streams
- Power estimation in combinational modules is addressed from a probabilistic point of view. The zero-delay hypothesis is considered and under highly correlated input streams, the ...
Radu Marculescu, Diana Marculescu, Massoud Pedram
HPCA
2008
IEEE
14 years 8 months ago
Performance and power optimization through data compression in Network-on-Chip architectures
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache ...
Reetuparna Das, Asit K. Mishra, Chrysostomos Nicop...
DAC
2000
ACM
14 years 3 days ago
Watermarking while preserving the critical path
In many modern designs, timing is either a key optimization goal and/or a mandatory constraint. We propose the first intellectual property protection technique using watermarking ...
Seapahn Meguerdichian, Miodrag Potkonjak
ENTCS
2008
91views more  ENTCS 2008»
13 years 7 months ago
Towards Concrete Syntax Patterns for Logic-based Transformation Rules
Logic meta-programming in Prolog is a powerful way to express program analysis and transformation. However, its use can be difficult and error-prone because it requires programmer...
Malte Appeltauer, Günter Kniesel