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» Power Optimized Combinational Logic Design
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DATE
2010
IEEE
119views Hardware» more  DATE 2010»
14 years 2 months ago
Exploiting local logic structures to optimize multi-core SoC floorplanning
Abstract—We present a throughput-driven partitioning algorithm and a throughput-preserving merging algorithm for the high-level physical synthesis of latency-insensitive (LI) sys...
Cheng-Hong Li, Sampada Sonalkar, Luca P. Carloni
CADE
1998
Springer
14 years 1 months ago
System Description: CRIL Platform for SAT
The CRIL multi-strategy platform for SAT includes a whole family of local search techniques and some of the best Davis and Putnam strategies for checking propositional satis abilit...
Bertrand Mazure, Lakhdar Sais, Éric Gr&eacu...
EUROGP
2001
Springer
124views Optimization» more  EUROGP 2001»
14 years 1 months ago
An Evolutionary Approach to Automatic Generation of VHDL Code for Low-Power Digital Filters
An evolutionary algorithm is used to design a finite impulse response digital filter with reduced power consumption. The proposed design approach combines genetic optimization an...
Massimiliano Erba, Roberto Rossi, Valentino Libera...
OSDI
2008
ACM
14 years 9 months ago
Delivering Energy Proportionality with Non Energy-Proportional Systems - Optimizing the Ensemble
: ? Delivering Energy Proportionality with Non Energy-Proportional Systems-Optimizing the Ensemble Niraj Tolia, Zhikui Wang, Manish Marwah, Cullen Bash, Parthasarathy Ranganathan, ...
Niraj Tolia, Zhikui Wang, Manish Marwah, Cullen Ba...
FPL
2005
Springer
115views Hardware» more  FPL 2005»
14 years 2 months ago
Statistical Power Estimation for FPGA
This article presents a power estimation tool integrated with an FPGA design flow. It is able to estimate total and individual-node average power consumption for combinational blo...
Elias Todorovich, Fabian Angarita, Javier Valls, E...