Sciweavers

430 search results - page 38 / 86
» Power Optimized Combinational Logic Design
Sort
View
ICCD
2005
IEEE
109views Hardware» more  ICCD 2005»
14 years 7 months ago
Optimizing the Thermal Behavior of Subarrayed Data Caches
Designing temperature-aware microarchitectures for microprocessors at new technologies is becoming a critical requirement due to the exponentially increasing on-chip power density...
Johnsy K. John, Jie S. Hu, Sotirios G. Ziavras
MICRO
2002
IEEE
128views Hardware» more  MICRO 2002»
14 years 3 months ago
Compiler-directed instruction cache leakage optimization
Excessive power consumption is widely considered as a major impediment to designing future microprocessors. With the continued scaling down of threshold voltages, the power consum...
Wei Zhang 0002, Jie S. Hu, Vijay Degalahal, Mahmut...
VLSID
2007
IEEE
210views VLSI» more  VLSID 2007»
14 years 10 months ago
Dynamically Optimizing FPGA Applications by Monitoring Temperature and Workloads
In the past, Field Programmable Gate Array (FPGA) circuits only contained a limited amount of logic and operated at a low frequency. Few applications running on FPGAs consumed exc...
Phillip H. Jones, Young H. Cho, John W. Lockwood
GLVLSI
2007
IEEE
115views VLSI» more  GLVLSI 2007»
14 years 4 months ago
Novel architectures for efficient (m, n) parallel counters
Parallel counters are key elements in many arithmetic circuits, especially fast multipliers. In this paper, novel architectures and designs for high speed, low power (3, 2), (7, 3...
Sreehari Veeramachaneni, Lingamneni Avinash, Kirth...
ISLPED
2006
ACM
83views Hardware» more  ISLPED 2006»
14 years 4 months ago
Considering process variations during system-level power analysis
Process variations will increasingly impact the operational characteristics of integrated circuits in nanoscale semiconductor technologies. Researchers have proposed various desig...
Saumya Chandra, Kanishka Lahiri, Anand Raghunathan...