430 search results - page 62 / 86 » Power Optimized Combinational Logic Design |
ISCAS
2006
IEEE
14 years 3 months ago
2006
IEEE
– Increasing logic densities and clock frequencies on FPGAs lead to rapid increase in power density, which translates to higher on-chip temperature. In this paper, we investigate...
GLVLSI
2003
IEEE
14 years 2 months ago
2003
IEEE
With scaling down to deep submicron and nanometer technologies, noise immunity is becoming a metric of the same importance as power, speed, and area. Smaller feature sizes, low vo...
ISLPED
2003
ACM
14 years 2 months ago
2003
ACM
This paper develops a technique that uniquely combines the advantages of static scheduling and dynamic scheduling to reduce the energy consumed in modern superscalar processors wi...
GECCO
2008
Springer
13 years 10 months ago
2008
Springer
In recent years, the development of multi-objective evolutionary algorithms (MOEAs) hybridized with mathematical programming techniques has significantly increased. However, most...
HIPC
2004
Springer
14 years 2 months ago
2004
Springer
This paper summarizes the design and implementation of a parallel algorithm for state assignment of large Finite State Machines (FSMs). High performance CAD tools are necessary to...