430 search results - page 73 / 86 » Power Optimized Combinational Logic Design |
ISQED
2005
IEEE
14 years 2 months ago
2005
IEEE
In this work, we present a genetic algorithm based thermal-aware floorplanning framework that aims at reducing hot spots and distributing temperature evenly across a chip while op...
MJ
2007
13 years 8 months ago
2007
With increasingly smaller feature sizes and higher on-chip densities, the power dissipation of VLSI systems has become a primary concern for designers. This paper first describes...
VLSID
2008
IEEE
14 years 9 months ago
2008
IEEE
Today's feature-rich multimedia products require embedded system solution with complex System-on-Chip (SoC) to meet market expectations of high performance at a low cost and l...
ESAS
2004
Springer
14 years 2 months ago
2004
Springer
The common perception of public key cryptography is that it is complex, slow and power hungry, and as such not at all suitable for use in ultra-low power environments like wireless...
DATE
2005
IEEE
14 years 2 months ago
2005
IEEE
Soft errors are an increasingly serious problem for logic circuits. To estimate the effects of soft errors on such circuits, we develop a general computational framework based on ...