430 search results - page 78 / 86 » Power Optimized Combinational Logic Design |
CF
2010
ACM
14 years 2 months ago
2010
ACM
We develop two simple interval-based models for dynamic superscalar processors. These models allow us to: i) predict with great accuracy performance and power consumption under va...
ISCA
2002
IEEE
14 years 1 months ago
2002
IEEE
An increasingly large portion of scheduler latency is derived from the monolithic content addressable memory (CAM) arrays accessed during instruction wakeup. The performance of th...
CLEF
2004
Springer
14 years 2 months ago
2004
Springer
Abstract. Recent research has suggested that there is no general similarity measure, which can be applied on arbitrary databases without any parameterization. Hence, the optimal co...
FAST
2011
13 years 12 days ago
2011
Multi-tier systems that combine SSDs with SAS/FC and/or SATA disks mitigate the capital cost burden of SSDs, while benefiting from their superior I/O performance per unit cost an...
VISUALIZATION
1992
IEEE
14 years 29 days ago
1992
IEEE
algorithms as networks of modules. The data flow architecture is popular because of the flexibility of mixing calculation modules with display modules, and because of its easy grap...