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DATE
2006
IEEE
71views Hardware» more  DATE 2006»
14 years 1 months ago
Exploring "temperature-aware" design in low-power MPSoCs
The power density inside high performance systems continues to rise with every process technology generation, thereby increasing the operating temperature and creating “hot spot...
Giacomo Paci, Paul Marchal, Francesco Poletti, Luc...
VLSI
2012
Springer
12 years 3 months ago
A Signature-Based Power Model for MPSoC on FPGA
e technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction than, for example, commonly used instruction-set sim...
Roberta Piscitelli, Andy D. Pimentel
HPCA
2008
IEEE
14 years 8 months ago
Performance and power optimization through data compression in Network-on-Chip architectures
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache ...
Reetuparna Das, Asit K. Mishra, Chrysostomos Nicop...
CODES
2011
IEEE
12 years 7 months ago
Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors
Today, mobile smartphones are expected to be able to run the same complex, memory-intensive applications that were originally designed and coded for general-purpose processors. Ho...
Garo Bournoutian, Alex Orailoglu
DATE
2002
IEEE
83views Hardware» more  DATE 2002»
14 years 18 days ago
Memory System Connectivity Exploration
In programmable embedded systems, the memory subsystem represents a major cost, performance and power bottleneck. To optimize the system for such different goals, the designer wou...
Peter Grun, Nikil D. Dutt, Alexandru Nicolau