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DAC
2006
ACM
14 years 8 months ago
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration
Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based ...
Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Ruten...
DAC
2007
ACM
14 years 8 months ago
Multi-Core Design Automation Challenges
The trend to multi-core chip designs presents new challenges for design automation, while the increased reuse of components may offer solutions. This paper describes some of the k...
John A. Darringer
HPCA
2001
IEEE
14 years 8 months ago
Dynamic Thermal Management for High-Performance Microprocessors
With the increasing clock rate and transistor count of today's microprocessors, power dissipation is becoming a critical component of system design complexity. Thermal and po...
David Brooks, Margaret Martonosi
VLSID
2007
IEEE
146views VLSI» more  VLSID 2007»
14 years 8 months ago
Architecting Microprocessor Components in 3D Design Space
Interconnect is one of the major concerns in current and future microprocessor designs from both performance and power consumption perspective. The emergence of three-dimensional ...
Balaji Vaidyanathan, Wei-Lun Hung, Feng Wang 0004,...
DAC
2009
ACM
14 years 2 months ago
Throughput optimal task allocation under thermal constraints for multi-core processors
It is known that temperature gradients and thermal hotspots affect the reliability of microprocessors. Temperature is also an important constraint when maximizing the performance...
Vinay Hanumaiah, Ravishankar Rao, Sarma B. K. Vrud...