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» Power Reduction in Large Fan-in CMOS Gates in Logic Arrays U...

140

GLVLSI
1997
IEEE

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Power Reduction in Large Fan-in CMOS Gates in Logic Arrays Using Selective Precharge

15 years 7 months ago

Power Reduction in Large Fan-in CMOS Gates in Logic Arrays Using Selective Precharge

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Shaoyi Wang

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170

FPGA
2003
ACM

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A scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS technology

15 years 8 months ago

A scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS technology

Download www.eecs.usma.edu

This paper presents a new power saving, high speed FPGA design enhancing a previous SiGe CML FPGA based on the Xilinx 6200 FPGA. The design aims at having a higher performance but...

Jong-Ru Guo, Chao You, Kuan Zhou, Bryan S. Goda, R...

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