13 search results - page 1 / 3 » Power and area optimization by reorganizing CMOS complex gat... |
ISLPED
1995
ACM
14 years 2 months ago
1995
ACM
Thispaper proposes a method for achieving low-power control-logic modules using a combination of CMOS complex gate reorganization, transistor size optimization, and transistor lay...
DATE
2006
IEEE
14 years 4 months ago
2006
IEEE
For CMOS technologies below 65nm, gate oxide direct tunneling current is a major component of the total power dissipation. This paper presents a simulated annealing based algorith...
ICCAD
1996
IEEE
14 years 3 months ago
1996
IEEE
In this paper we present an ecient technique to reduce the switching activity in a CMOS combinational logic network based on local logic transformations. These transformations con...
ICCAD
1997
IEEE
14 years 3 months ago
1997
IEEE
High-level power estimation, when given only a high-level design specification such as a functional or RTL description, requires high-level estimation of the circuit average acti...
ISPD
2012
ACM
12 years 6 months ago
2012
ACM
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...