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DATE
2003
IEEE
65views Hardware» more  DATE 2003»
14 years 3 months ago
Masking the Energy Behavior of DES Encryption
Smart cards are vulnerable to both invasive and non-invasive attacks. Specifically, non-invasive attacks using power and timing measurements to extract the cryptographic key has d...
Hendra Saputra, Narayanan Vijaykrishnan, Mahmut T....
GLVLSI
2010
IEEE
210views VLSI» more  GLVLSI 2010»
14 years 3 months ago
Overscaling-friendly timing speculation architectures
Processors have traditionally been designed for the worst-case, resulting in designs that have high yields, but are expensive in terms of area and power. Better-than-worst-case (B...
John Sartori, Rakesh Kumar
ISCA
2002
IEEE
91views Hardware» more  ISCA 2002»
14 years 2 months ago
Slack: Maximizing Performance Under Technological Constraints
Many emerging processor microarchitectures seek to manage technological constraints (e.g., wire delay, power, and circuit complexity) by resorting to nonuniform designs that provi...
Brian A. Fields, Rastislav Bodík, Mark D. H...
PDCN
2004
13 years 11 months ago
Scalable parallel algorithms for difficult combinatorial problems: A case study in optimization
A novel combination of emergent algorithmic methods, powerful computational platforms and supporting infrastructure is described. These complementary tools and technologies are us...
Faisal N. Abu-Khzam, Michael A. Langston, Pushkar ...
ISPASS
2005
IEEE
14 years 3 months ago
Partitioning Multi-Threaded Processors with a Large Number of Threads
Today’s general-purpose processors are increasingly using multithreading in order to better leverage the additional on-chip real estate available with each technology generation...
Ali El-Moursy, Rajeev Garg, David H. Albonesi, San...